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Integrated Circuit Systems, Inc.
ICS8520
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
FEATURES
* 16 differential LVHSTL compatible outputs each with the ability to drive 50 to ground * 1 differential CLK, nCLK input pair * CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL * Maximum output frequency: 500MHz * Translates single ended input levels to LVHSTL levels with resistor bias nCLK input * Output skew: 110ps (maximum) * Part-to-part skew: 450ps (maximum) * Propagation delay: 1.6ns (maximum) * VOH: 1.3V (maximum) * 40% of VOH Vcrossover 60% of VOH * 3.3V core, 1.8V output operating supply voltages * 0C to 70C ambient operating temperature
GENERAL DESCRIPTION
The ICS8520 is a low skew, high performance 1-to-16 Differential-to-LVHSTL Fanout Buffer and HiPerClockSTM a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8520 has 1 clock input pair. The CLK, nCLK pair can accept most standard differential input levels.
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Guaranteed output skew, part-to-part skew and crossover voltage characteristics make the ICS8520 ideal for interfacing to today's most advanced microprocessor and static RAMs.
BLOCK DIAGRAM
CLK nCLK
PIN ASSIGNMENT
nCLK VDDO Q15 nQ15 Q14 nQ14 GND Q13 nQ13 Q12 nQ12 VDDO
Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5 Q6 nQ6 Q7 nQ7
Q15 nQ15 Q14 nQ14 Q13 nQ13 Q12 nQ12 Q11 nQ11 Q10 nQ10 Q9 nQ9 Q8 nQ8
VDDO Q11 nQ11 Q10 nQ10 GND Q9 nQ9 Q8 nQ8 VDDO VDD
48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24
ICS8520
CLK VDDO nQ0 Q0 nQ1 Q1 GND nQ2 Q2 nQ3 Q3 VDDO
48-Lead LQFP 7mm x 7mm x 1.4mm body package Y Package Top View
8520DY
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VDDO nQ4 Q4 nQ5 Q5 GND nQ6 Q6 nQ7 Q7 VDDO VDD
REV. A NOVEMBER 12, 2002
Integrated Circuit Systems, Inc.
ICS8520
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Type Power Output Output Power Output Output Power Output Output Output Output Output Output Output Output Input Input Output Output Output Output Pullup Description Output supply pins. Differential output pair. LVHSTL interface levels. Differential output pair. LVHSTL interface levels. Power supply ground. Differential output pair. LVHSTL interface levels. Differential output pair. LVHSTL interface levels. Core supply pins. Differential output pair. LVHSTL interface levels. Differential output pair. LVHSTL interface levels. Differential output pair. LVHSTL interface levels. Differential output pair. LVHSTL interface levels. Differential output pair. LVHSTL interface levels. Differential output pair. LVHSTL interface levels. Differential output pair. LVHSTL interface level Differential output pair. LVHSTL interface level Pulldown Non inver ting differential clock input. Inver ting differential clock input. Differential output pair. LVHSTL interface levels. Differential output pair. LVHSTL interface levels. Differential output pair. LVHSTL interface levels. Differential output pair. LVHSTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 11, 14, 24, 25, 35, 38, 48 2, 3 4, 5 6, 19, 30, 43 7, 8 9, 10 12, 13 15, 16 17, 18 20, 21 22, 23 26, 27 28, 29 31, 32 33, 34 36 37 39, 40 41, 42 44, 45 46, 47 Name VDDO Q11, nQ11 Q10, nQ10 GND Q9, nQ9 Q8, nQ8 VDD Q7, nQ7 Q6, nQ6 Q5, nQ5 Q4, nQ4 Q3, nQ3 Q2, nQ2 Q1, nQ1 Q0, nQ0 CLK nCLK Q15, nQ15 Q14, nQ14 Q13, nQ13 Q12, nQ12
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 51 51 Maximum 4 Units pF K K
TABLE 3. FUNCTION TABLE
Inputs CLK 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nCLK 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 Q0:Q15 LOW HIGH LOW HIGH HIGH LOW Outputs nQ0:nQ15 HIGH LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting
NOTE 1: Please refer to the Application Information Section, "Wiring the Differential input to accept single ended levels".
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REV. A NOVEMBER 12, 2002
Integrated Circuit Systems, Inc.
ICS8520
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol VDD VDDO IDD IDDO Parameter Positive Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 1.6 Typical 3.3 1.8 Maximum 3.465 2.0 190 10 Units V V mA A
TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current CLK nCLK CLK nCLK Test Conditions VIN = VDD = 3.465V VIN = VDD = 3.465V VIN = 0V, VDD = 3.465V VIN = 0V, VDD = 3.465V -1 -150 1.3 VDD - 0.85 Minimum Typical Maximum 150 1 Units A A A A V V
Peak-to-Peak Input Voltage 0.15 Common Mode Voltage Range; VCMR GND + 0.5 NOTE 1, 2 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.
TABLE 4C. LVHSTL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol Parameter Output High Voltage; VOH NOTE 1 Output Low Voltage; VOL NOTE 1 Output Crossover Voltage VOX Test Conditions Minimum 0.9 0 40% x (VOH-VOL) + VOL Typical Maximum 1.3 0.4 60% x (VOH-VOL) + VOL Units V V V
NOTE 1: Outputs terminated with 50 to ground.
8520DY
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REV. A NOVEMBER 12, 2002
Integrated Circuit Systems, Inc.
ICS8520
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Test Conditions Minimum 1.1 Typical 1.3 Maximum 500 1.6 110 450 900 600 52 54 58 Units MHz ns ps ps ps ps % % %
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol fMAX tPD tsk(o) tsk(pp) Parameter Output Frequency Propagation Delay, Low-to-High; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4
400MHz 300MHz 200 Output Rise/Fall Time tR/tF > 300MHz 200 133MHz 48 odc Output Duty Cycle 133MHz < 300MHz 46 > 300MHz 42 NOTE 1: Measured from the differential input crossing point to the differential ouput crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8520DY
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REV. A NOVEMBER 12, 2002
Integrated Circuit Systems, Inc.
ICS8520
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
1.8V0.2V 3.3V5%
VDD VDD VDDO
Qx
SCOPE
nCLK
V
PP
LVHSTL
nQx
Cross Points
V
CMR
CLK
GND GND = 0V
3.3V/1.8V OUTPUT LOAD AC TEST CIRCUIT
nQx Qx nQy Qy
tsk(o)
DIFFERENTIAL INPUT LEVEL
Qx PART 1 nQx Qy PART 2 nQy
tsk(pp)
OUTPUT SKEW
PART-TO-PART SKEW
nCLK
80% 80% V 20% Clock Outputs t
R SW I N G
CLK nQ0:nQ15 Q0:Q15
tPD
20% t
F
OUTPUT RISE/FALL TIME
nQ0:nQ15 Q0:Q15
Pulse Width t
PERIOD
PROPAGATION DELAY
odc =
t PW t PERIOD
odc & tPERIOD
8520DY
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REV. A NOVEMBER 12, 2002
Integrated Circuit Systems, Inc.
ICS8520
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8520. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS8520 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 190mA = 658.4mW Power (outputs)MAX = 32.6mW/Loaded Output pair If all outputs are loaded, the total power is 16 * 32.6mW = 521.6mW
Total Power_MAX (3.465V, with all outputs switching) = 658.4mW + 521.6mW = 1180mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 1.18W * 42.1C/W = 119.7C. This is below the limit of 125C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE qJA
FOR
48-PIN LQFP, FORCED CONVECTION
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8520DY
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REV. A NOVEMBER 12, 2002
Integrated Circuit Systems, Inc.
ICS8520
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVHSTL output driver circuit and termination are shown in Figure 1.
VDDO
Q1
VOUT RL 50
FIGURE 1. LVHSTL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load.
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Pd_H = (V
OH_MIN
/R ) * (V
L DDO_MAX
-V
OH_MIN
) )
Pd_L = (V
OL_MAX
/R ) * (V
L DDO_MAX
-V
OL_MAX
Pd_H = (0.9V/50) * (2V - 0.9V) = 19.8mW Pd_L = (0.4V/50) * (2V - 0.4V) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32.6mW
8520DY
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REV. A NOVEMBER 12, 2002
Integrated Circuit Systems, Inc.
ICS8520
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 7.
JAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0 200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
67.8C/W 47.9C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8520 is: 1563
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REV. A NOVEMBER 12, 2002
Integrated Circuit Systems, Inc.
ICS8520
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
PACKAGE OUTLINE - Y SUFFIX
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L q ccc 0.45 0 --0.05 1.35 0.17 0.09 BBC MINIMUM NOMINAL 48 --1.40 0.22 -9.00 BASIC 7.00 BASIC 5.50 Ref. 9.00 BASIC 7.00 BASIC 5.50 Ref. 0.50 BASIC 0.60 --0.75 7 0.08 1.60 0.15 1.45 0.27 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
8520DY
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REV. A NOVEMBER 12, 2002
Integrated Circuit Systems, Inc.
ICS8520
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Marking ICS8520DY ICS8520DY Package 48 Lead LQFP 48 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature 0C to 70C 0C to 70C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS8520DY ICS8520DYT
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8520DY
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REV. A NOVEMBER 12, 2002

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